1. Field of the Invention
The present invention relates generally to packaging substrates, fabrication methods thereof and base materials, and more particularly, to a low-cost packaging substrate and a fabrication method thereof.
2. Description of Related Art
Along with the development of electronic industries, electronic products have a trend towards miniaturization and high performance, and accordingly multi-layer boards are developed so as to increase the layout area for the layout through interlayer connection techniques, meet demands for high-density integrated circuits, and reduce the thickness of packaging substrates.
Conventionally, a multi-layer board comprises a core board and built-up structures formed on two sides of the core board. However, the use of the core board increases the length of wires and thickness of the overall structure. Accordingly, coreless boards are developed to shorten the length of wires and reduce the thickness of the overall structure, thereby meeting the developmental trend of high frequency and miniaturization.
FIGS. 1A to 1F shows a conventional packaging substrate and a method for fabricating the same.
Referring to FIG. 1A, a carrier board 10 is provided, and a thin metal layer 11, a releasing layer 12 and a carrier metal layer 13 are formed in sequence on the two surfaces of the carrier board 10.
Referring to FIG. 1B, a first dielectric layer 14 is formed on the carrier metal layer 13.
Referring to FIG. 1C, a plurality of vias 140 are formed in the first dielectric layer 14 through a photolithography process or laser ablation, and portions of the carrier metal layer 13 exposed from the vias 140 are etched away so as to form a plurality of concave portions 130.
Referring to FIG. 1D, a plurality of solder bumps 141a and first conductive vias 141b are formed in sequence in the concave portions 130 and the corresponding vias 140, and a first wiring layer 142 is formed on the first dielectric layer 14 and electrically connected to the first conductive vias 141b. A built-up structure 15 is formed on the first dielectric layer 14, wherein the built-up structure 15 comprises at least a second dielectric layer 151, a second wiring layer 152 formed on the second dielectric layer 151, and a plurality of second conductive vias 153 formed in the second dielectric layer 151 and electrically connecting the first wiring layer 142 and the second wiring layer 152. The second wiring layer 152 disposed on an outermost portion of the built-up structure 15 has a plurality of conductive pads 154. An insulating protective layer 16 is formed on an outermost portion of the built-up structure 15. A plurality of openings 160 corresponding in position to the conductive pads 154, respectively, are formed in the insulating protective layer 16 so as for the conductive pads 154 to be exposed from the insulating protective layer 16.
Referring to FIG. 1E, the releasing layer 12 is separated from the carrier metal layer 13 so as to separate packaging substrates to be formed subsequently from the carrier board 10.
Referring to FIG. 1F, the carrier metal layer 13 is removed such that the solder bumps 141a protrude from the surface of the first dielectric layer 14 to thereby allow a semiconductor chip (not shown) to be mounted thereto.
As described above, the releasing layer 12 made of metal is formed on both sides of the carrier board 10, then the built-up structure 15 is formed on the releasing layer 12 on both sides, and finally the built-up structure 15 at the two sides of the carrier board 10 is separated along the interface between the releasing layer 12 and the carrier metal layer 13 so as to from two packaging substrates.
However, in the above method, the carrier board 10 and the thin metal layer 11 required for temporarily supporting the structure complicate the fabrication process. Also, the temporary carrier (including the carrier board 10, the thin-film metal layer 11 and the releasing layer 12) is finally discarded, which results in a waste of materials and increase of fabrication costs.
Therefore, it is imperative to overcome the above drawbacks of the prior art.